Classifications Of Sequential Circuits:
The sequential circuits are classified on the basis of timing of their signals into two types. They are,
1) Synchronous sequential circuit.
2) Asynchronous sequential circuit.
There are two types of sequential circuit, synchronous and asynchronous.Synchronous types use pulsed or level inputs and a clock input to drive the circuit (with restrictions on pulse width and circuit propagation)
Asynchronous sequential circuits do not use a clock signal as synchronous circuits do. Instead the circuit is driven by the pulses of the inputs.
A pulsed output is an output that lasts for the duration of a particular input pulse but can be less in some cases. For the clocked sequential circuits, the output pulse is the same duration as the clock pulse.A level output refers to an output that changes state at the start of an input pulse or clock pulse and remains in that state until the next input or clock pulse.
5.2 Basic Flip-Flops, Truth Tables And Excitation Tables (Nand Rs Latch, Nor Rs Latch, Rs Flip-Flop, Jk Flip-Flop, t Flip-Flop, d Flip-Flop With Reset And Clear Terminals).
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information.
A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs.
The flip-flop is an important element of such circuits.
The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state.
Different Types Of Flip-Flop:
There are various types of flip flops. Some of them are mentioned below. They are,
• RS flip-flop
• SR flip-flop
• D flip-flop
• JK flip-flop
• T flip-flop
SR flip flop:
The circuit remains in a particular output state indefinitely until something is done to change its output status. If the LOW and HIGH outputs are respectively regarded as 0 and 1, then the output can either be a 0 or a 1.
Since either a 0 or a 1 can be held indefinitely until the circuit is appropriately triggered to go to the other state, the circuit is said to have memory. It is capable of storing one binary digit or one bit of digital information.
Also, if we recall the functioning of the bi stable multivibrator circuit, we find that, when one of the transistors was in saturation, the other was in cut-off.
This implies that if we had the outputs from the collectors of both the transistors, then the two outputs would be complementary.
In the flip-flops of various types that are available in IC form, we will see that all these devices offer complementary outputs usually designated as Q and Q‘.
The R-S flip-flop is the most basic of all flip-flops. The letters R and S here stand for RESET and SET.
When the flip-flop is SET, its Q output goes to a 1 state, and when it is RESET it goes to a 0 state. The Q output is the complement of the Q output at all times.
Operation of RS flip-flop:
When R input is low and S input is high, the Q output of flip-flop is set.
When R input is high and S input is low, the Q output of flip-flop is reset.
When both the inputs R and S are low, the output does not change.
When both the inputs R and S are high, the output is unpredictable.
S R Q(t + 1) A B Y
0 0 Indeterminate 0 0 1
0 1 Set 0 1 1
1 0 Reset 1 0 1
1 1 NC 1 1 0
Logic diagram of SR flip-flop
JK flip flop:
A J-K flip-flop behaves in the same fashion as an R-S flip-flop except for one of the entries in the function table.
In case of R-S flip-flop, its input combination S = R = 1 (in the case of a flip-flop with active HIGH inputs) and the input combination S = R = 0 (in the case of a flip-flop with active LOW inputs) are prohibited.
In the case of a J-K flip-flop with active HIGH inputs, the output of the flip-flop toggles, that is, it goes to the other state, for J = K = 1 .
The output toggles for J = K = 0 in the case of the flip-flop having active LOW inputs. Thus, the J-K flip-flop can overcome the problem of a forbidden input combination of the R-S flip-flop.
Figures below show the circuit symbol of level-triggered J-K flip-flops with active HIGH and active LOW inputs respectively with their function tables.
The characteristic tables for a J-K flip-flop with active HIGH J and K inputs and a J-K flip-flop with active LOW J and K inputs respectively are shown in both Figures (a) and (b).
The corresponding Karnaugh maps are shown in below figure for the characteristics table .
The characteristic equations for the Karnaugh maps of below figure is shown next.
a) JK flip flop with active high inputs, b) JK flip flop with active low inputs
JK flip-flop is an universal flip-flop:
When configured in various ways, JK flip flop is capable of operating like most other types of flip – flops.
Operation of JK flip-flop:
When K input is low and J input is high, the Q output of flip-flop is set.
When K input is high and J input is low, the Q output of flip-flop is reset.
When both the inputs K and J are low, the output does not change.
When both the inputs K and J are high, it is possible to set or reset the flip-flop (i.e) the output toggle on the next positive clock edge.
Q J K Q(t + 1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Counter using JK flip flop:
Q2 Q1 Q0
0 0 0
0 0 1
0 1 1
1 1 1
1 1 0
1 0 0
0 0 0
PS NS JK Input
Q2 Q1 Q0 Q0 + 1 Q2 + 1 Q1 + 1 J2 K2 J1 K1 J0 Ko
0 0 0 1 0 0 0 X 0 X 1 X
0 0 1 1 0 1 0 X 1 X X 0
0 1 0 0 0 0 0 X X 1 0 X
0 1 1 1 1 1 1 X X 0 X 0
1 0 0 0 0 0 X 1 0 X 0 X
1 0 1 0 0 0 X 1 0 X X 1
1 1 0 0 1 0 X 0 X 1 0 X
1 1 1 0 1 1 X 0 X 0 X 1
K – Map:
Let us consider that The following sequence is to be realized by a counter consisting of 3 JK Flip flops.
A1 0 0 0 0 1 1 0
A2 0 1 1 0 0 1 0
A3 0 1 0 1 1 0 0
Here we will design the counter.
Present State Next State Flip-Flop Inputs
A1 A2 A3 A1 A2 A3 JA1 KA1 JA2 KA2 JA3 KA3
0 0 0 0 1 1 0 X 1 X 1 X
0 1 1 0 1 0 0 X X 0 X 1
0 1 0 0 0 1 0 X X 1 1 X
0 0 1 1 0 1 1 X 0 X X 0
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 0 0 0 X 1 X 1 0 X
K – map:
A D flip-flop also called a delay flip-flop can be used to provide temporary storage of one bit of information.
Figure shows the symbol of the circuit and the function table of a negative edge-triggered D flip-flop.
When the clock is active, the data bit (0 or 1) present at the D input is transferred to the output.In the D flip-flop, the data transfer from D input to Q output occurs on the negative-going (HIGH-to-LOW) transition of the clock input. D input can acquire new status.
(a) Symbol, (b) Function table, (c) Truth table and (d) K-Map
Operation of D flip-flop:
In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset.
Q D Q(t + 1)
0 0 0
0 1 1
1 0 0
1 1 1
Flip-Flop excitation tables for D flip-flop:
In D flip-flop, its next state is always equal to the D input and it is independent of the present state.
D is 0 if Qn+1 has to 0 and if Qn+1 has to be 1 regardless the value of Qn.
The output of a toggle flip-flop also called a T flip-flop changes state every time it is triggered at its T input called the toggle input. That is, its output becomes 1, if it was 0 and 0 if it was 1.
If we consider the T input as active when HIGH, the characteristic table of such a flip-flop is shown in the figure. The Karnaugh maps for the characteristic tables of Figures are shown . The characteristic equations as written from the Karnaugh maps are as follows:
Operation of T flip-flop:
T flip-flop is also known as Toggle flip-flop.
When the value of T=0, there is no change in the output.
When the value of T=1, the output switch to the complement state (i.e) the output toggles.
Flip-flop excitation tables for T flip-flop:
When input T=1 the state of the flip-flop is complemented.
when T=0, the state of the Flip-flop remains unchanged. Therefore, for 0_0 and 1_1 transitions T must be 0 and for 0_1 and 1_0 transitions must be 1.
Master-Slave JK Flip-flop:
A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave.
The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series configuration with the slave having an inverted clock pulse.
The outputs from Q and Q from the “Slave” flip-flop are fed back to the inputs of the “Master” with the outputs of the “Master” flip flop being connected to the two inputs of the “Slave” flip flop. This feedback configuration from the slave’s output to the master’s input gives the characteristic toggle of the JK flip flop as shown below.
Master-Slave JK Flip Flop
The input signals J and K are connected to the gated “master” SR flip flop which “locks” the input condition while the clock (Clk) input is “HIGH” at logic level “1”.
As the clock input of the “slave” flip flop is the inverse (complement) of the “master” clock input, the “slave” SR flip flop does not toggle.
The outputs from the “master” flip flop are only “seen” by the gated “slave” flip flop when the clock input goes “LOW” to logic level “0”.
When the clock is “LOW”, the outputs from the “master” flip flop are latched and any additional changes to its inputs are ignored.
The gated “slave” flip flop now responds to the state of its inputs passed over by the “master” section.
Then ,on the “Low-to-High” transition of the clock pulse ,the inputs of the “master” flip flop are fed to the gated inputs of the “slave” flip flop and on the “High-to-Low” transition, the same inputs are reflected on the output of the “slave” making this type of flip flop edge or pulse-triggered.
Then, the circuit accepts input data when the clock signal is “HIGH” and passes the data to the output on the falling-edge of the clock signal.
In other words, the Master-Slave JK Flip flop is a “Synchronous” device as it only passes data with the timing of the clock signal.
Application of Master Slave FF:
• Frequency dividers
• Shift registers
• Parallel data storage
5.3 Conversion From One Flip-Flop To Flip-Flop
JK Flip Flop to SR Flip Flop:
S and R will be the external inputs to J and K. As shown in the logic diagram below, J and K values will be the outputs of the combinational circuit. Thus, the values of J and K have to be obtained in terms of S, R and Qp. The logic diagram is shown below.
A conversion table is to be written using S, R, Qp, Qp+1, J and K. For two inputs S and R, eight combinations can be made. For each combination, its corresponding Qp+1 outputs are found out.
The outputs for the combinations of S=1 and R=1 are not permitted for an SR flip flop. Hence, the outputs are considered as invalid and the J and K values are taken as “don’t cares”.
Conversion table, K-Map and Logic diagram
SR Flip Flop to D Flip Flop:
As shown in the figure, S and R are the actual inputs of the flip flop and D is the external input of the flip flop. The four combinations, the logic diagram, conversion table and the K-map for S and R in terms of D and Qp are shown below.
Conversion table, K-Map and Logic diagram
D Flip Flop to SR Flip Flop:
D is the actual input of the flip flop and S and R are the external inputs. Eight possible combinations are achieved from the external inputs S, R and Qp. Since the combination of S=1 and R=1 are invalid, the values of Qp+1 and D are considered as “don’t cares”.
The logic diagram showing the conversion from D to SR, and the K-map for D in terms of S, R and Qp are shown below.
Conversion table, K-Map and Logic diagram
JK Flip Flop to T Flip Flop:
J and K are the actual inputs of the flip flop and T is taken as the external input for conversion. Four combinations are produced with T and Qp. J and K are expressed in terms of T and Qp.
Conversion table, K-Map and Logic diagram
5.4 Design Of Ripple Counters,Design Of Synchronous Counters, Johnson Counter, Ring Counter
A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are also called ripple-counters because of the way the clock pulse ripples it way through the flip-flops.
The MOD of the ripple counter or asynchronous counter is 2n if n flip-flops are used. For a 4-bit counter, the range of the count is 0000 to 1111 (24-1). A counter may count up or count down or count up and down depending on the input control. The count sequence usually repeats itself. When counting up, the count sequence goes from 0000, 0001, 0010, … 1110 , 1111 , 0000, 0001, … etc. When counting down the count sequence goes in the opposite manner: 1111, 1110, … 0010, 0001, 0000, 1111, 1110, … etc.
The complement of the count sequence counts in reverse direction. If the uncomplemented output counts up, the complemented output counts down. If the uncomplemented output counts down, the complemented output counts up.
There are many ways to implement the ripple counter depending on the characteristics of the flip flops used and the requirements of the count sequence.
Clock Trigger: Positive edged or Negative edged
JK or D flip-flops
Count Direction: Up, Down, or Up/Down
Asynchronous counters are slower than synchronous counters because of the delay in the transmission of the pulses from flip-flop to flip-flop. With a synchronous circuit, all the bits in the count change synchronously with the assertion of the clock. Examples of synchronous counters are the Ring and Johnson counter.
It can be implemented using D-type flip-flops or JK-type flip-flops.
The circuit below uses 2 D flip-flops to implement a divide-by-4 ripple counter (2n = 22 = 4). It counts down.
Synchronous Counter Design
A finite-state machine determines its outputs and its next state from its current inputs and current state. A synchronous finite state machine changes state only when the appropriate clock edge occurs.
The following diagram shows a sequential circuit that consists of a combinational logic block and a memory block. For simplicity, we limit the design to one input and 2 JK flip flops. You will learn to derive the combination logic that meets the design specifications.
The steps to design a Synchronous Counter using JK flip flops are:
Let us describe a general sequential circuit in terms of its basic parts and its input and outputs.
Let us design a 2 bit up/down counter with an input D which determines the up/down function. Thus when D=0, the count sequence is 00,01,10,11,00 … when D=1, the count sequence is 00,11,10,01,00 …
Draw the state diagram for the given sequence.
Develop a next-state table for the specific counter sequence. Using the state diagram as a reference, fill up the present state and next state columns. For this interactive table, we can modify the next state.
Present State Next State JK flip flop inputs
D QA QB QA QB JA KA JB KB
0 0 0 0 1 0 X 1 X
0 0 1 1 0 1 X X 1
0 1 0 1 1 X 0 1 X
0 1 1 0 0 X 1 X 1
1 0 0 1 1 1 X 1 X
1 0 1 0 0 0 X X 1
1 1 0 0 1 X 1 1 X
1 1 1 1 0 X 0 X 1
JK Flip Flop Truth Table
J K Q
0 0 Qo
0 1 0
1 0 1
1 1 Toggle
JK Flip Flop Transition Table
QN QN+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Use K-map to derive the logic equations.
JA = D QB + D QB
QAQB \\ D 0 1
00 0 1
01 1 0
11 X X
10 X X
KA = D QB + D QB
QAQB \\ D 0 1
00 X X
01 X X
11 1 0
10 0 1
JB = 1
QAQB \\ D 0 1
00 1 1
01 X X
11 X X
10 1 1
KB = 1
QAQB \\ D 0 1
00 X X
01 1 1
11 1 1
10 X X
Use the boolean expressions to implement the counter
Shift register counters – Ring counter
A shift register can also be used as a counter. A shift register with the serial output connection back to the serial input is called Shift register counter.
There are 2 types of shift Register counters are:
i) Ring counter
ii) Johnson counter
A ring counter is a circular shift register with only one flip flop being set at any particular time, all others are cleared.
A ring counter is a counter that counts up and when it reaches the last number that is designed to count up , it will reset itself back to the first number.
For example, a ring counter that is designed using 3 JK Flip Flops will count starting from 001 to 010 to 100 and back to 001. It will repeat itself in a ‘Ring’
The Johnson counter is a K-bit switch-tail ring counter with 2k decoding gates to provide outputs for 2 k timing signals
A Johnson counter is a special case of shift register where, the output from the last stage is inverted and fed back as input to the first stage. A pattern of bits equal in length to the shift register thus circulates indefinitely. These counters are sometimes called “walking ring” counters.
It is used in specialist applications including those similar to the decade counter, digital to analogue conversion, etc.and thus the name Ring Counter.
5.5 Design Of Registers – Buffer Register, Control Buffer Register, Shift Register, Bi-Directional Shift Register, Universal Shift Register
Figure below shows the simplest register constructed with four D flip-flops. This register is also called buffer register. Each D flip-flop is triggered with a common negative edge clock pulse. The input X bits set up the flip-flops for loading.
Therefore, when the first negative clock edge arrives, the stored binary information becomes,
In this register, four D flip-flops are used. So it can store 4-bit binary information. Thus the number of flip-flop stages in a register determines its total storage capacity.
Controlled Buffer Register
We can control input and output of the register by connecting tristate devices at the input and output sides of register as shown in Figure below .So this register is called ‘controlled buffer register’. Here, tristate switches are used to control the operation. When we want to store data in the register, we have to make LOAD or WR signal low to activate the tristate buffers.
When we want the data at the output, we have to make RD signal low to activate the buffers.
Controlled Buffer Register
Controlled buffer registers are commonly used for temporary storage of data within a digital system.
A register capable of shifting its binary information in one or both directions from state to state within the register or into or out of the register upon application of clock pulses is called a shift register.
A register that is capable of shifting data, one bit at a time is called a shift register. One of the uses of a shift register is to convert between serial and parallel interfaces.
This is useful as many circuits work on groups of bits in parallel, but serial interfaces are simpler to construct.
Shift registers can be used as simple delay circuits and also as pulse extenders. A serial shift register consists of a chain of flip-flops connected in cascade with the output of one flip-flop being connected to the input of its neighbor.
The operation of the shift register is synchronous; thus each flip-flop is connected to a common clock.
D flip-flops forms the simplest type of shift-registers. The basic data movements possible within a four-bit shift register is shown in figure.
Timing diagram of shift register
The types of shift registers are:
1) Serial In Serial Out (SISO)
2) Serial In Parallel Out (SIPO)
3) Parallel In Serial Out (PISO)
4) Parallel In Parallel Out (PIPO)
Serial-In, Serial-Out :
In destructive readout – each datum is lost once it has been shifted out of the right-most bit.
These are the simplest kind of shift register. The data string is presented at ‘Data In’, and is shifted right one stage each time ‘Data Advance’ is brought high.
At each advance, the bit on the far left (i.e. ‘Data In’) is shifted into the first flip-flop’s output. The bit on the far right (i.e. ‘Data Out’ ) is shifted out and lost.
Non-destructive readout can be achieved if another input line is added – the Read/Write Control.
When this is high (i.e. write) then the shift register behaves as normal, advancing the input data one place for every clock cycle and data can be lost from the end of the register.
However, when the R/W control is set low (i. e. read), any data shifted out of the register at the right becomes the next input at the left and is kept in the system.
Therefore, as long as the R/W control is set low, none of the data can be lost from the system.
This configuration allows conversion from serial to parallel format.
Data are input serially and once the data has been input, it may be either read off at each output simultaneously or it can be shifted out and replaced.
This configuration has the data input in parallel format. To write the data to the register, the Write/Shift control line must be held LOW.
To shift the data, the W/S control line is brought HIGH and the registers are clocked.
As long as the number of clock cycles is not more than the length of the data-string, the Data Output, Q, will be the parallel data read off in order.
This kind of shift register takes the data from the parallel inputs (D0-D3) and shifts it to the corresponding output (Q0-Q3) when the registers are clocked.
It can be used as a kind of ‘history ‘ retaining old information as the input in another part of the system until ready for new information,where upon the registers are clocked and the new data are ‘let through’.
Bidirectional Shift Register
This type of register allows shifting of data either to the left or to the right side. It can be implemented by using logic gate circuitry that enables the transfer of data from one stage to the next stage to the right or to the left, depending on the level of a control line. Figure below shows a four-bit bidirectional register.
4-bit bi-directional shift register
The RIGHT/LEFT is the control input signal which allows data shifting either towards right or towards left. A high on this line enables the shifting of data towards right and a low enables it towards left. When RIGHT/LEFT signal is high, gates GI, G2, G3, G4 are enabled. The state of the Q output of each flip-flop is passed through the D input of the following flip-flop.
When a clock pulse arrives, the data are shifted one place to the right. When the RIGHT/LEFT signal is low, gates G5, Gs, G7, G5 are enabled. The Q output of each flip-flop is passed through the D input of the preceding flip-flop. When clock pulse arrives, the data are shifted one place to the left. Bidirectional Shift Register with Parallel Load We have seen that shift register can be used for converting serial data into parallel data, and vice-versa.
When parallel load capability is added to the shift register, the data entered in parallel can be taken out in serial fashion by shifting the data stored in the register. Such a register is called bidirectional shift register with parallel load. Figure below shows bidirectional shift register with parallel load.
As shown in the Figure (b) , the D input of each flip-flop has three sources :
Output of left adjacent flip-flop
output of right adjacent flip-flop and
Out of these three sources one source is selected at a time and it is done with the help of decoder. The decoder select lines (SL1 and SL0) select the one source out of three as shown in the table below.
When select lines are 00 (i.e. SL1 = 0 and SL0 = 0), data from the parallel inputs is loaded into the 4-bit register. When select lines are 01 (i.e. SL1 = 0 and SL0 = 1), data within the register is shifted 1-bit left. When select lines are 10 (i.e. SL1 = 1 and SL0 = 0), data within the register is shifted 1-bit right.
(b) 4-bit bi-directional shift register with parallel load
Universal shift registers
Today, there are many high speed bi-directional “universal” type Shift Registers available such as the TTL 74LS194, 74LS195 or the CMOS 4035 which are available as 4-bit multi-function devices that can be used in either serial-to-serial, left shifting, right shifting, serial-to-parallel, parallel-to-serial or as a parallel-to-parallel multi-function data register, hence the name “Universal”.
These universal shift registers can perform any combination of parallel and serial input to output operations but require additional inputs to specify desired function and to pre-load and reset the device. A commonly used universal shift register is the TTL 74LS194.
4-bit Universal Shift Register 74LS194
Universal shift registers are very useful digital devices. They can be configured to respond to operations that require some form of temporary memory storage or for the delay of information such as the SISO or PIPO configuration modes or transfer data from one point to another in either a serial or parallel format.
Universal shift registers are frequently used in the arithmetic operations to shift data to the left or right for multiplication or division.