Multi-level inverters can benefit from reduced output filter size and smaller harmonic contents. It’s disadvantage is caused by the high number of switching elements usually needed. In order to reduce the number of used switches in a sevenlevel inverter, a new topology approach is presented. This article analyzes theoretically its operational principles and switching logic. The circuit results in a single-phase evenly spaced sevenlevel pulse width modulation inverter using only six switches and two voltage sources. Finally, the proposed topology’s validity and switching pattern equations are verified through model’s simulation. Multi-level inverters purpose is to synthesize a high power alternate voltage or current source using a series of power semiconductor switches with one or several dc voltage sources to perform the power conversion by switching a staircase voltage waveform [1].
The higher the number of levels, more similar its unfiltered output will be to the desired waveform reference. The performance of multilevel inverters enhances as the number of levels of the inverter increases [2] and its total harmonic distortion (THD) is reduced [3]. Multi-level inverters have the advantage of reducing the harmonic contents in the load currents and filters size in high power applications for its lower voltage rate of change dv=dt applied to the output [4].
Nowadays it is well established that multi-level inverters are the most suitable choice in high power applications [5]. Being able to change their switching frequency and their output waveform frequency, these pulse width modulation (PWM) inverters are suitable for some high power industrials applications such as AC motor speed control, uninterruptible power supplies [6], pumps [7] and fans (used in water, oil and gas plants, cooling systems, geothermal power plants, furnaces and boilers), power quality conditioners [8] and adjustable speed drives [2]. There are three main topologies that can be used to generate a seven-level inverter [4]: (a) Cascaded H-brigde (CHB), in witch H-brigde cells with an isolated power source have their output connected in series [8]; (b) Neutral-Point-Clamped (NPC) or diode-clamped [7], a simplification of the cascaded topology; and (c) Flying Capacitor (FC) or capacitor-clamped, where capacitors have their references changed in an orderly way to create the voltage divisions needed [9].
One clear disadvantage in such inverters is the increased number of active switches and the cost added by its drivers and complex switching pattern [1], [10]. NPC and FC also needs careful control over the capacitors charge and voltage division. All three topologies need twelve switches for a seven-level inverter, and at least three capacitors [11]. In addition, several isolated voltages sources are normally needed to achieve a higher number of voltage levels, which increases the circuit complexity [12]. However, using a lower number of switches and the correct voltage relation between sources, the scheme and costs can be simplified. Some simplified seven-level inverter topologies have already been proposed. A two cascated H-bridges with two diferent voltage sources making a seven-level inverter, using eight switches, is proposed by [2]. A packed U cells (PUC) was proposed by [11], using six switches a voltage source and a capacitor that needs to be correctly charged. A modified Hbridge is shown by [13]. It has six switches, but need three capacitors besides the voltage source, but it is possible to reduce the number of capacitors to two with the addition of a transformer to charge them [14]. In the following sections another approach to the seven-level inverter is presented, as a symmetrical improvement of the five-level inverter proposed by [6], by adding one bidirectional switch between the center tap of the sources and the second inverter leg, adding up to only six switches and two voltages sources needed. The principles of operation and the logic equations to command the switches are theoretically analyzed and explained giving a solid base to a model implementation. The inverter simulation demonstrates its feasibility and validates the switches command scheme proposed. II. PROPOSED INVERTER The proposed inverter shown in Fig. 1 presents two voltage sources V1 and V2 in series, where V2 must have double the voltage of V1. There are four switches (Q1 to Q4) in a full bridge configuration. Two bidirectional switches (Q5 and Q6) are added between each full bridge’s leg and the voltage sources center-tap. With this implementation, each point A or B in the circuit can be tapped to 0 Volts, V1 or V1 + V2. A RL load is connected in between the points A and B. With the correct switches configuration for each leg, it is possible to obtain seven different voltage levels at the load terminals A and B determined by the points voltage difference: V1 + V2, V2, V1, 0 Volts, ??V1, ??V2 and ??(V1 + V2). The Table I presents all the valid switches states and their related output voltage at the load terminal. The ON state is denoted by ‘1’ and the OFF state by ‘0’. A positive output current Io is represented in the Table I by I+ and its negative value by I??. States witch implies a source short circuit were left out of the table and some particularities were also remarked. It must be noted that on each non-zero voltage level, there is always only two active switches in the circuit. By analyzing the difference between adjacent voltage levels it is possible to define the how to command the switches to achieve a PWM transition between these levels, as shown in Table II. In this table, an increase of the duty-cycle D complexity [12]. However, using a lower number of switches and the correct voltage relation between sources, the scheme and costs can be simplified. Some simplified seven-level inverter topologies have already been proposed. A two cascated H-bridges with two diferent voltage sources making a seven-level inverter, using eight switches, is proposed by [2]. A packed U cells (PUC) was proposed by [11], using six switches a voltage source and a capacitor that needs to be correctly charged. A modified Hbridge is shown by [13]. It has six switches, but need three capacitors besides the voltage source, but it is possible to reduce the number of capacitors to two with the addition of a transformer to charge them [14].
In the following sections another approach to the seven-level inverter is presented, as a symmetrical improvement of the five-level inverter proposed by [6], by adding one bidirectional switch between the center tap of the sources and the second inverter leg, adding up to only six switches and two voltages sources needed. The principles of operation and the logic equations to command the switches are theoretically analyzed and explained giving a solid base to a model implementation. The inverter simulation demonstrates its feasibility and validates the switches command scheme proposed. II. PROPOSED INVERTER The proposed inverter shown in Fig. 1 presents two voltage sources V1 and V2 in series, where V2 must have double the voltage of V1. There are four switches (Q1 to Q4) in a full bridge configuration. Two bidirectional switches (Q5 and Q6) are added between each full bridge’s leg and the voltage sources center-tap. With this implementation, each point A or B in the circuit can be tapped to 0 Volts, V1 or V1 + V2. A RL load is connected in between the points A and B. With the correct switches configuration for each leg, it is possible to obtain seven different voltage levels at the load terminals A and B determined by the points voltage difference: V1 + V2, V2, V1, 0 Volts, ??V1, ??V2 and ??(V1 + V2). The Table I presents all the valid switches states and their related output voltage at the load terminal. The ON state is denoted by ‘1’ and the OFF state by ‘0’. A positive output current Io is represented in the Table I by I+ and its negative value by I??. States witch implies a source short circuit were left out of the table and some particularities were also remarked. It must be noted that on each non-zero voltage level, there is always only two active switches in the circuit. By analyzing the difference between adjacent voltage levels it is possible to define the how to command the switches to achieve a PWM transition between these levels, as shown in Table II. In this table, an increase of the duty-cycle D is responsible for an increase in the output voltage value between the voltage levels in the respective mode. In fact, as D increases linearly from 0 to 1, so does the output voltage between the mode minimum and maximum voltages. The duty-cycle complement is represented as D0. Even with different number of switching elements in each mode, only two switches remains conducting even for the zero voltage output, since a bidirectional freewheel state was selected for modes A and D (zero voltage output). The Fig. 2 shows the cases (a) to (i) described in the Table I. For each case, the current path is draw in order to show to applied voltage to the output. Cases (k) to (q) are valid, but not demonstrated as they are not used in this proposition. A. Inverter Waveforms The Fig. 3 shows the principal waveforms that explains the inverter functionality. The sinusoidal reference Vref with an amplitude Vp is compared against 6 triangular carriers (CarrierA to CarrierF ), each with an amplitude equal to V1, one for each mode and between its voltage levels. The output voltage Vo is generated with the correct comparisons and switches conditions. The comparators Ca to Cf output values are high when Vref is higher than the respective carrier and low otherwise. Six different periods P1 to P6 constitute the full pattern. They are the periods where each mode is active in the inverter. The equations are explained next. B. Switching Equations In order to have the desired output voltage in their load terminals, the switches are in the position designated by Table I. Given that Vp is bigger than V2, the angles 1 to Finally, the switching function for every switch Q1 ?? Q6 can be derived from logical AND, NOT and OR gates, using the information from the carriers comparators and the periods where they are ON, OFF or switching: In order to validate the proposed multilevel inverter, the PSIM software has been used to simulate the circuit presented in Fig. 1. The used values for the circuit elements were V1 = 100V , V2 = 200V , Vref = 200Vrms, and a 1kVA RL load with a power factor of 0.8 (R = 32:00 , L = 63:67mH). The reference frequency was 60Hz and the switching frequency was 20kHz. The results are presented in Fig. 4. It can be seen that the output current is sinusoidal (measured THD is 0.0893%) and that the switching follows the desired reference. No anomalies were detected. The circuit output voltage was also modeled in function of the switching pattern and simulated in a Cyclone IV FPGA. The voltage output was acquired in raw and low-pass filtered formats and are shown in Fig. 5. The proposed topology for a single-phase evenly spaced seven-level PWM inverter have the advantage of having only six switches and only two conducting at any time. Despite that two voltage sources are needed, they are connected in series so they don’t need to be isolated from each other as in other approaches. Another advantage is that the switching pattern act directly to in the output voltage and it is easy to be implemented as there is no need to balance capacitor voltages. The numeric simulations validate the modeled inverter functionality, but further experimental results are still needed to obtain the inverter efficiency.
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